1. Field of the Invention
The present invention relates to imaging systems and, in particular, to imaging systems which increase photodetector charge capacity towards the end of the integration period to extend the dynamic range of the imaging system.
2. Description of the Related Art
The entire disclosure of U.S. patent application Ser. No. 09/087,087, filed May 29, 1998, is expressly incorporated by reference herein
Various types of imagers (also sometimes referred to as image sensors) are in use today, including charge-coupled device (CCD) imagers and complementary metal-oxide semiconductor (CMOS) imagers. These devices are typically incorporated into CCD and CMOS imaging systems, respectively. Such imaging systems comprise an array of pixels, each of which contains a light-sensitive sensor element such as a CCD or, in CMOS imagers, a N+ to p-substrate photodiode, a virtual gate buried n-channel photodetector, or a photogate detector. Such light-sensitive sensor elements will be referred to herein, generally, as photodetectors.
CMOS imagers typically utilize an array of active pixel sensors and a row (register) of correlated double-sampling (CDS) circuits or amplifiers to sample and hold the output of a given row of pixel imagers of the array. Each active pixel typically contains a pixel amplifying device (usually a source follower). The term active pixel sensor (APS) refers to electronic image sensors within active devices, such as transistors, that are associated with each pixel. CMOS imagers are often interchangeably referred to as CMOS APS imagers or as CMOS active pixel imagers. The active pixel sensors and accompanying circuitry for each pixel of the array will be referred to herein as APS circuits or APS pixel circuits.
In both CMOS and CCD imager systems, each photodetector accumulates charge and hence voltage during the optical integration period in accordance with the light intensity reaching the relevant sensing area of the photodetector. As charge accumulates, the photodetector begins to fill. The charge stored in a photodetector is sometimes said to be stored in the xe2x80x9ccharge wellxe2x80x9d of CCD-type photodetectors. If the photodetector becomes full of charge, then excess charge is shunted off to a xe2x80x9cblooming drain,xe2x80x9d in part to prevent blooming. Blooming is a phenomenon in which excess charge beyond pixel saturation spills over into adjacent pixels, causing blurring and related image artifacts. In a CMOS system, the voltage of, for example, the photodiode, falls in accordance with the negative charge. However, if the photodetector becomes full before the end of the integration period and any additional photons strike the photodetector, then no additional charge can be accumulated (in the case of CMOS, the diode voltage cannot fall any lower). Thus, for example, if very bright light is applied to a photodetector, this can cause the photodetector to be full before the end of the integration period and thus to saturate and lose information.
Each APS circuit produces an output signal at the end of an integration period, which is related to the amount of charge accumulated during the integration period. The amount of charge is in turn related to the amount of light received by the photodetector of the APS circuit during the integration period. The output signal may be sampled and held by a CDS circuit, and then applied to a buffer for signal processing.
U.S. Pat. No. 3,953,733, issued Apr. 27, 1976 to Levine (xe2x80x9cLevinexe2x80x9d), the entirety of which is incorporated herein by reference, teaches a method of operating CCD imagers to avoid this problem. The voltage applied to the electrodes of a CCD cause a heavily depleted region to form beneath the electrode, which forms xe2x80x9cpotential wellsxe2x80x9d or charge wells of a given maximum charge capacity. A greater electrode voltage causes a correspondingly greater charge capacity well to form. The voltage that controls the maximum charge capacity of a photodetector, such as the CCD electrode voltage, will be referred to herein as the charge capacity control voltage, and the maximum charge that can be accumulated in a photodetector will be referred to herein as the photodetector""s charge capacity. The charge capacity control voltage is also sometimes referred to as the blooming barrier voltage, since it acts as a blooming drain to remove charge from the pixel photodiode to avoid charge spilling into adjacent pixels during optical overload.
Typically, the charge capacity control voltage applied is constant throughout the integration period, so that a given charge capacity exists throughout the integration period for each pixel of the imager array. In Levine, the charge capacity control voltage is varied during the integration period, so as to increase the optical dynamic range of the CCD imager. Levine thus teaches an extended dynamic range (XDR) system. For example, in one embodiment, Levine teaches increasing the charge capacity control voltage (and hence the charge capacity) in non-linear fashion, by increasing the charge capacity control voltage in discrete steps towards the end of the integration period. Levine also teaches other methods of increasing the charge capacity control voltage and charge capacity towards the end of the integration period to extend the dynamic range of the imaging system, such as using enough multiple discrete steps to implement a continuously increasing charge capacity control voltage; or using linearly increasing charge capacity control voltage waveforms and increasing the slope or slopes of such waveforms.
In a CMOS XDR imager system, each photodetector of the array of photodetectors is configured so as to accumulate charge up to a first maximum charge capacity during a first, majority portion of the integration period. This may be done by resetting a photodiode voltage to an initial voltage at the beginning of the integration period. The voltage then decreases from the initial level as charge accumulates. At a time before the end integration period, the photodiode voltage is pulled up to a second level, in case it has been saturated (i.e., is below the second level). This thus clears the pixel of signal beyond the second level, which allows more charge to be accumulated for the remainder of the integration period. This effectively provides a first charge capacity during the first part of the integration period and an additional charge capacity for the remainder thereof.
Very bright light will thus saturate during the first period and will accumulate again during the second period. The point between the first portion of the integration period and the remainder when saturation occurs (and thus XDR is utilized) may be referred to as the breakpoint. The first portion and charge accumulated during the first portion are associated with a xe2x80x9clinearxe2x80x9d range, and the remainder portion and any excess charge accumulated during this remainder portion are associated with an xe2x80x9cextendedxe2x80x9d dynamic range. The linear range has higher sensitivity than the XDR, but the XDR allows at least some contrast to be measured for higher light levels that otherwise would have saturated the linear range.
The total accumulated charge may be read out at the end of the integration period by a CDS circuit or other suitable means, which samples and holds the output of a given photodetector of the array. This may be converted to a digital number representative of the total charge. Standard mathematical techniques may then be applied to this information, based on the ratio of the two time periods and related information, to determine the total overall light that has impinged on the corresponding photodetector during the integration period.
CMOS imagers have several advantages over CCD imagers. For example, CCD imagers are not easily integrated with CMOS process peripheral circuitry due to complex fabrication requirements and relatively high cost. By contrast, since CMOS imagers are formed with the same CMOS process technology as the peripheral circuitry required to operate the CMOS imager, such sensors are easier to integrate into a single system-on-chip using integrated circuit (IC) fabrication processes. By using CMOS imagers, it is possible to have monolithic integration of control logic and timing, image processing, and signal-processing circuitry such as analog-to-digital (A/D) conversion, all within a single sensor chip. Thus, CMOS imagers can be manufactured at low cost, relative to CCD imagers, using standard CMOS IC fabrication processes.
Additionally, CCD imagers typically require three different input voltages with separate power supplies to drive them. CCD imagers also require relatively high power supply voltages and thus also require relatively high power to operate. By contrast, CMOS devices require only a single power supply, which may also be used to drive peripheral circuitry. This gives CMOS imagers an advantage in terms of power consumption and external circuitry complexity, and also in terms of the amount of chip area or xe2x80x9creal-estatexe2x80x9d devoted to power supplies. CMOS imagers have relatively low power requirements because of the relatively low voltage power supply required for operation, and also because only one row of pixels in the APS array needs to be active during readout.
Despite these advantages, however, CMOS imagers also have various disadvantages in comparison to CCD imagers. For example, in CMOS systems there may be mismatches between components of the APS pixel circuits. Such variations in components can cause different photodetectors to have different breakpoints. For example, in a CMOS imager system, the charge capacity of a photodetector may be switched from the first maximum charge capacity to the second maximum charge capacity by use of a reset transistor. (I.e., the reset transistor is used to bring the photodiode voltage up to an initial voltage and then to a second voltage level.) The reset transistors may each have a different threshold associated therewith, which can cause the breakpoint to vary somewhat from the ideal. For example, in CMOS imagers, breakpoints may vary up to approximately 10% to 15% from ideal.
The variation of breakpoints among pixels of the array can give rise to various artifacts, such as the xe2x80x9cpuddlingxe2x80x9d and xe2x80x9cdirty windowxe2x80x9d artifacts. Puddling is a xe2x80x9cfixed patternxe2x80x9d artifact in which some neighboring pixels appear relatively bright and others relatively dim, since they are produced by falling into the linear or extended dynamic ranges. This causes a structure much like a winding river-type shape to be visible between pixel regions in the linear range and those in the XDR. The dirty window artifact arises in areas of relatively high intensity which utilize the extended dynamic range of the system, since each one may have slightly different DC offsets due to the different breakpoints. This latter artifact is also due in part to the fact that, during linearization of the non-linear piece-wise signal, the XDR components are multiplied by an integer, e.g. on the order of 9, to match the slope of the linear portion, which also multiplies such breakpoint-caused differences in the XDR portions.
Conventional approaches to addressing such problems are not always satisfactory. For example, a frame memory may be utilized to attempt to reduce such artifacts, by correcting for such fixed pattern differences between pixels of the array. However, such approaches may be expensive, complex, or otherwise undesirable in certain applications. Further, some breakpoint and other components or characteristics between pixels may vary with temperature or other variable parameters, making frame memory solutions more complex and expensive, or even unworkable.
An extended dynamic range imager. In one embodiment, an array of pixels provides an output signal for each pixel related to an amount of light captured for each pixel during an integration period. A row of extended dynamic range (XDR) sample and hold circuits having an XDR sample and hold circuit for each column of the array captures an XDR signal related to a difference between the output signal and an XDR clamp level to which the pixel is reset at a predetermined time before the end of the integration period. A row of linear sample and hold circuits having a linear sample and hold circuit for each column of the array captures a linear signal related to a difference between the output signal and an initial output signal to which the pixel is reset at the beginning of the integration period.